The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
A protocol, referred to as either the hopping bus protocol or the MoChi protocol, has been developed for optimizing the efficiency of intra-chip and inter-chip communications of Systems-on-Chip (“SoCs”). Background of how the hopping bus protocol enables intra-chip and inter-chip communications between discrete SoCs and their components is described in commonly-assigned U.S. Patent Publication 2015/0169495), the contents of which are hereby incorporated by reference herein in their entirety.
Under the hopping bus protocol an individual chip or SoC may be an application processor (e.g., a CPU) or a peripheral and may include processing circuitry that assigns and decodes addresses or identifiers for each chip or SoC. The chips or SoCs can thereby communicate, so that each chip or SoC serves as a module of a larger system-on-multiple-modular-chips. Within such a system, each modular chip is provided with a certain number of upstream interfaces, and a certain number of downstream interfaces, which may limit how the modules can be interconnected to form a system-on-modular-multiple-chips.